MCP23008 IO Expander - Interrupt control

I found the interupt logic of MCP23008 and MCP23017 are similar, except perhaps MCP23017 is a superset of MCP23008.  So I just read MCP23017 but would test on MCP23008.






MCP23017 Interrupt logic (from datasheet)


* Configurable interrupt output pins

- Configurable as active-high, active-low or open-drain

* INTA and INTB can be configured to operate independently or together

* Configurable interrupt source

- Interrupt-on-change from configured register defaults or pin changes

* Polarity Inversion register to configure the polarity of the input port data

There are two interrupt pins, INTA and INTB, that can be associated with their respective ports, or can be logically OR’ed together so that both pins will activate if either port causes an interrupt.

The interrupt output can be configured to activate under two conditions (mutually exclusive):

1. When any input state differs from its corresponding Input Port register state. This is used to indicate to the system master that an input state has changed.

2. When an input state differs from a preconfigured register value (DEFVAL register).

The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition
that caused the interrupt.

1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER

The GPINTEN register controls the interrupt-onchange feature for each pin.

If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change.

bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change bits <7:0>

1 = Enable GPIO input pin for interrupt-on-change event.

0 = Disable GPIO input pin for interrupt-on-change event.

1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE

The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur.

bit 7-0 DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from defaults <7:0>.
If the associated pin level is the opposite from the register bit, an interrupt occurs.

1.6.5 INTERRUPT CONTROL REGISTER

The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature.

If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.

bit 7-0 IOC7:IOC0: These bits control how the associated pin value is compared for interrupt-on-change <7:0>

1 = Controls how the associated pin value is compared for interrupt-on-change.

0 = Pin value is compared against the previous pin value.

1.6.6 CONFIGURATION REGISTER

The IOCON register contains several bits for configuring the device:

The MIRROR bit controls how the INTA and INTB pins function with respect to each other.

* When MIRROR = 1, the INTn pins are functionally OR’ed so that an interrupt on either port will cause both pins to activate.

* When MIRROR = 0, the INT pins are separated.

Interrupt conditions on a port will cause its respective INT pin to activate.

The Open-Drain (ODR) control bit enables/disables the INT pin for open-drain configuration. Erasing this bit overrides the INTPOL bit.

The Interrupt Polarity (INTPOL) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull.

bit 6 MIRROR: INT Pins Mirror bit

1 = The INT pins are internally connected

0 = The INT pins are not connected. INTA is associated with PortA and INTB is associated with PortB

bit 2 ODR: This bit configures the INT pin as an open-drain output.

1 = Open-drain output (overrides the INTPOL bit).

0 = Active driver output (INTPOL bit sets the polarity).

bit 1 INTPOL: This bit sets the polarity of the INT output pin.

1 = Active-high.

0 = Active-low.

1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER

The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 kΩ resistor.

bit 7-0 PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input) <7:0>.

1 = Pull-up enabled.

0 = Pull-up disabled.

1.6.8 INTERRUPT FLAG REGISTER

The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt.

This register is ‘read-only’. Writes to this register will be ignored.

bit 7-0 INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>.

1 = Pin caused interrupt.

0 = Interrupt not pending.

1.6.9 INTERRUPT CAPTURE REGISTER

The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO.

bit 7-0 ICP7:ICP0: These bits reflect the logic level on the port pins at the time of interrupt due to pin change <7:0>

1 = Logic-high.

0 = Logic-low.


1.7 Interrupt Logic

If enabled, the MCP23X17 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. Each pin is individually configurable as follows:

* Enable/disable interrupt via GPINTEN

* Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt-on-Change (IOC).

The interrupt control module uses the following registers/bits:

* IOCON.MIRROR – controls if the two interrupt pins mirror each other

* GPINTEN – Interrupt enable register

* INTCON – Controls the source for the IOC

* DEFVAL – Contains the register default for IOC operation


1.7.1 INTA AND INTB

There are two interrupt pins: INTA and INTB. By default, INTA is associated with GPAn pins (PortA) and INTB is associated with GPBn pins (PortB). Each porthas an independent signal which is cleared if its associated GPIO or INTCAP register is read.

1.7.1.1 Mirroring the INT pins

Additionally, the INTn pins can be configured to mirror each other so that any interrupt will cause both pins to go active. This is controlled via IOCON.MIRROR.

If IOCON.MIRROR = 0, the internal signals are routed independently to the INTA and INTB pads.

If IOCON.MIRROR = 1, the internal signals are OR’ed together and routed to the INTn pads. In this case, the interrupt will only be cleared if the associated GPIO or INTCAP is read (see Table 1-7).

TABLE 1-7: INTERRUPT OPERATION
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1.7.2 IOC FROM PIN CHANGE

If enabled, the MCP23X17 will generate an interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC enabled pins will be compared. Refer to Register 1-3 and Register 1-5.

1.7.3 IOC FROM REGISTER DEFAULT

If enabled, the MCP23X17 will generate an interrupt if a mismatch occurs between the DEFVAL register and the port.
Only IOC enabled pins will be compared.
Refer to Register 1-3, Register 1-5 and Register 1-4.

1.7.4 INTERRUPT OPERATION

The INTn interrupt output can be configured as activelow, active-high or open-drain via the IOCON register.

Only those pins that are configured as an input (IODIR register) with Interrupt-On-Change (IOC) enabled (IOINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt output pin.

Input change activity on a port input pin that is enabled for IOC will generate an internal device interrupt and the device will capture the value of the port and copy it into INTCAP. The interrupt will remain active until the INTCAP or GPIO register is read. Writing to these registers will not affect the interrupt. The interrupt condition will be cleared after the LSb of the data is clocked out during a read command of GPIO or INTCAP.

The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO.

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Note: The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update.

1.7.5 INTERRUPT CONDITIONS

There are two possible configurations that cause interrupts (configured via INTCON):

1. Pins configured for interrupt-on-pin change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs and after clearing the interrupt condition (i.e., after reading GPIO or INTCAP). For example, an interrupt occurs by an input changing from ‘1’ to ‘0’. The new initial state for the pin is a logic 0 after the interrupt is cleared.

2. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTCAP or GPIO is read.

See Figure 1-6 and Figure 1-7 for more information on interrupt operations.

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