XiLinx XC9500 CPLD learning notes

CPLD Complex programmable logic device - Wikipedia

A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.


Features in common with PALs

Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up.

For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

Features in common with FPGAs

Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.

Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.


Non-volatility

The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.


Distinctions

CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in turn were preceded by standard logic products, that offered no programmability and were "programmed" by wiring several standard logic chips together.


The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (for example, sum of products).


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Xilinx ISE - Wikipedia

Xilinx ISE

Developer(s) Xilinx

Initial release 2003?

Stable release 14.4 / December 18, 2012; 2 months ago

Written in polylingual

Operating system RHEL, SLED, FreeBSD, & Microsoft Windows (XP Professional & 7 Professional)

Platform 32 bits & 64 bits

Size 5.8 Gigabytes

Available in English

Type EDA

License Proprietary

Website http://www.xilinx.com/tools/webpack.htm

Xilinx ISE[1] is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Web Edition is a free version of Xilinx ISE that can be downloaded at no charge. This edition provides synthesis and programming for a limited number of Xilinx devices. In particular devices with a large number of I/O pins and large gate matrices are disabled.

The low-cost Spartan family of FPGAs is fully supported by this edition, as well as the family of CPLDs, meaning small developers and educational institutions have no overheads from the cost of development software.

License registration is required to use the Web Edition of Xilinx ISE, which is free and can be renewed an unlimited number of times.

The 14.4 version released in 2012-12-18 and the GNU/Linux version has a size of 5.8 GB (update size needed).

Xilinx ISE Subscription Edition

Subscription Edition is also available for free download, but a license must be paid for to use the full functionality in the software. The free Web Edition license can be used with this software, restricting the devices that can be used.

Supported chips

ISE Design suite device support

ISE Webpack Tool

(free) ISE Design suite

(pay)

...

XC9500 Series CPLD All (Except 9500XV family)


Compatibility


GNU/Linux

Although Xilinx only officially supports Red Hat Enterprise 4, 5, & 6 Workstations (32 & 64 bits) & SUSE Linux Enterprise 11 (32 & 64 bits),[4] many other version of GNU/Linuxes can support Xilinx ISE WebPack with some modifications or configurations.[5][6][7] FreeBSD has the capability to run the Xilinx ISE WebPack by setting the OS environment variable to "Linux".[8] Xilinx's forums has these suggestions:
http://www.xilinx.com/support/answers/20944.htm

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