Microchip MCP413X/415X/423X/425X 7/8-Bit Single/Dual SPI Digital POT with Volatile Memory
Features
• Single or Dual Resistor Network options
• Potentiometer or Rheostat configuration options
• Resistor Network Resolution
- 7-bit: 128 Resistors (129 Steps)
- 8-bit: 256 Resistors (257 Steps)
• RAB Resistances options of:
- 5kΩ
- 10kΩ
- 50kΩ
- 100 kΩ
• Zero Scale to Full-Scale Wiper operation
• Low Wiper Resistance: 75Ω (typical)
• Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
• SPI Serial Interface (10 MHz, modes 0,0 & 1,1)
- High-Speed Read/Writes to wiper registers
- SDI/SDO multiplexing (MCP41X1 only)
• Resistor Network Terminal Disconnect Feature
via:
- Shutdown pin (SHDN)
- Terminal Control (TCON) Register
• Brown-out reset protection (1.5V typical)
• Serial Interface Inactive current (2.5 uA typical)
• High-Voltage Tolerant Digital Inputs: Up to 12.5V
• Supports Split Rail Applications
• Internal weak pull-up on all digital inputs
• Wide Operating Voltage:
- 2.7V to 5.5V - Device Characteristics
Specified
- 1.8V to 5.5V - Device Operation
• Wide Bandwidth (-3 dB) Operation:
- 2 MHz (typical) for 5.0 kΩ device
• Extended temperature range (-40°C to +125°C)
Description
The MCP41XX and MCP42XX devices offer a wide range of product offerings using an SPI interface. This family of devices support 7-bit and 8-bit resistor
networks, and Potentiometer and Rheostat pinouts.
4.0 FUNCTIONAL OVERVIEW
This Data Sheet covers a family of thirty-two Digital Potentiometer and Rheostat devices that will be referred to as MCP4XXX. The MCP4XX1 devices are
the Potentiometer configuration, while the MCP4XX2 devices are the Rheostat configuration.
As the Device Block Diagram shows, there are four main functional blocks. These are:
• POR/BOR Operation
• Memory Map
• Resistor Network
• Serial Interface (SPI)
The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and SPI operation are described in their own sections. The
Device Commands commands are discussed in Section 7.0.
5.2 Wiper
Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper) pin.
A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of
000h). A full-scale connections, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h).
In these configurations the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches.
A wiper setting value greater than full-scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full-Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map.
Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B.
A POR/BOR event will load the Volatile Wiper register value with the default value. Table 5-2 shows the default values offered.
6.0 SERIAL INTERFACE (SPI)
The MCP4XXX devices support the SPI serial protocol. This SPI operates in the slave mode (does not generate the serial clock).
The SPI interface uses up to four pins. These are:
• CS - Chip Select
• SCK - Serial Clock
• SDI - Serial Data In
• SDO - Serial Data Out
Typical SPI Interfaces are shown in Figure 6-1. In the SPI interface, The Master’s Output pin is connected to the Slave’s Input pin and the Master’s Input pin is connected to the Slave’s Output pin.
The MCP4XXX SPI’s module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1.
The SPI mode is determined by the state of the SCK pin (VIH or VIL) on the when the CS pin transitions from inactive (VIH) to active (VIL or VIHH).
All SPI interface signals are high-voltage tolerant.
6.1.3.1 SDI/SDO Operation
Figure 6-2 shows a block diagram of the SDI/SDO pin. The SDI signal has an internal “smart” pull-up. The value of this pull-up determines the frequency that data can be read from the device. An external pull-up can be added to the SDI/SDO pin to improve the rise time and therefore improve the frequency that data can be read.
Data written on the SDI/SDO pin can be at the maximum SPI frequency.
On the falling edge of the SCK pin during the C0 bit (see Figure 7-1), the SDI/SDO pin will start outputting the SDO value. The SDO signal overrides the control of the smart pull-up, such that whenever the SDI/SDO pin is outputting data, the smart pull-up is enabled.
The SDI/SDO pin will change from an input (SDI) to an output (SDO) after the state machine has received the Address and Command bits of the Command Byte. If
the command is a Read command, then the SDI/SDO pin will remain an output for the remainder of the command. For any other command, the SDI/SDO pin
returns to an input.
FIGURE 6-2: Serial I/O Mux Block Diagram.
Note: MCP41X1 Devices Only .
Note: To support the High voltage requirement of the SDI function, the SDO function is an open drain output.
Note: Care must be take to ensure that a Drive conflict does not exist between the Host Controllers SDO pin (or software SDI/SDO pin) and the MCP41x1 SDI/SDO pin (see Figure 6-1).
6.2 The SPI Modes
The SPI module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The mode is determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.2.1 MODE 0,0
In Mode 0,0: SCK idle state = low (VIL), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.
6.2.2 MODE 1,1
In Mode 1,1: SCK idle state = high (VIH), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.
6.3 SPI Waveforms
Figure 6-3 through Figure 6-8 show the different SPI command waveforms. Figure 6-3 and Figure 6-4 are read and write commands. Figure 6-5 and Figure 6-6
are read commands when the SDI and SDO pins are multiplexed on the same pin (SDI/SDO). Figure 6-7 and Figure 6-8 are increment and decrement commands.
7.0 DEVICE COMMANDS
The MCP4XXX’s SPI command format supports 16 memory address locations and four commands. Each command has two modes. These are:
• Normal Serial Commands
• High-Voltage Serial Commands
Normal serial commands are those where the CS pin is driven to VIL. High Voltage Serial Commands, CS pin is driven to VIHH, for compatibility with systems that also support the MCP414X/416X/424X/426X devices. High Voltage Serial Commands operate identically to their corresponding Normal Serial Command. In each
mode, there are four possible commands. These commands are shown in Table 7-1.
The 8-bit commands (Increment Wiper and Decrement Wiper commands) contain a Command Byte, see Figure 7-1, while 16-bit commands (Read Data and Write Data commands) contain a Command Byte and a Data Byte. The Command Byte contains two data bits, see Figure 7-1.
Table 7-2 shows the supported commands for each memory location and the corresponding values on the SDI and SDO pins.
Table 7-3 shows an overview of all the SPI commands and their interaction with other device features.
7.1 Command Byte
The Command Byte has three fields, the Address, the Command, and 2 Data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). This is for the Write command.
The device memory is accessed when the master sends a proper Command Byte to select the desired operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The action desired is contained in the Command Byte’s C1:C0 bits, see Table 7-1. C1:C0 determines if the
desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers.
As the Command Byte is being loaded into the device (on the SDI pin), the device’s SDO pin is driving. The SDO pin will output high bits for the first six bits of that command. On the 7th bit, the SDO pin will output the CMDERR bit state (see Section 7.3 “Error Condition”).
The 8th bit state depends on the the command selected.
TABLE 7-1: COMMAND BIT OVERVIEW
FIGURE 7-1: General SPI Command Formats.
C1:C0 Bit
States Command # of Bits
11 Read Data 16-Bits
00 Write Data 16-Bits
01 Increment 8-Bits
10 Decrement 8-Bits
7.2 Data Byte
Only the Read Command and the Write Command use the Data Byte, see Figure 7-1. These commands concatenate the 8-bits of the Data Byte with the one
data bit (D8) contained in the Command Byte to form 9-bits of data (D8:D0). The Command Byte format supports up to 9-bits of data so that the 8-bit resistor
network can be set to Full-Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B.
The D9 bit is currently unused, and corresponds to the position on the SDO data of the CMDERR bit.
7.4 Continuous Commands
The device supports the ability to execute commands continuously. While the CS pin is in the active state (VIL or VIHH). Any sequence of valid commands may be received.
The following example is a valid sequence of events:
1. CS pin driven active (VIL or VIHH).
2. Read Command.
3. Increment Command (Wiper 0).
4. Increment Command (Wiper 0).
5. Decrement Command (Wiper 1).
6. Write Command.
7. Write Command.
8. CS pin driven inactive (VIH).
TABLE 7-3: COMMANDS
Note
1: It is recommended that while the CS pin is active, only one type of command should be issued. When changing commands, it is recommended to take the CS pin inactive then force it back to the activestate.
2: It is also recommended that long command strings should be broken down into shorter command strings. This reduces the probability of noise on the
SCK pin corrupting the desired SPI command string.
Command Name # of Bits High Voltage (VIHH) on CS pin?
Write Data 16-Bits —
Read Data 16-Bits —
Increment Wiper 8-Bits —
Decrement Wiper 8-Bits —
High Voltage Write Data 16-Bits Yes
High Voltage Read Data 16-Bits Yes
High Voltage Increment Wiper 8-Bits Yes
High Voltage Decrement Wiper 8-Bits Yes
7.5 Write Data Normal and High Voltage
...
7.6 Read Data Normal and High Voltage
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7.7 Increment Wiper Normal and High Voltage
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7.7.2 CONTINUOUS INCREMENTS Continuous Increments are
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7.8 Decrement Wiper Normal and High Voltage
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7.8.2 CONTINUOUS DECREMENTS
Continuous Decrements are possible only when writing to the wiper registers. Figure 7-9 shows a continuous Decrement sequence for three continuous writes. The writes do not need to be to the same volatile memory address.
When executing an continuous Decrement commands, the selected wiper will be altered from n to n-1 for each Decrement command received. The wiper value will
decrement from the wipers Full-Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full-Scale value (8-bit =101h to 1FFh,
7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See
Table 7-4 for additional information on the Decrement Command vs. the current volatile wiper value.
Decrement commands can be sent repeatedly without raising CS until a desired condition is met. The value in the Volatile Wiper register can be read using a Read Command.
When executing a continuous command string, The Decrement command can be followed by any other valid command.
The wiper terminal will move after the command has been received (8th clock).
After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that “unexpected” transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs.
8.0 APPLICATIONS EXAMPLES
Digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming.
The MCP413X/415X/423X/425X devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V).
8.2 Techniques to force the CS pin to VIHH
The circuit in Figure 8-3 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC® microcontrollers (MCUs) IO2 pin.
When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the CS pin to go higher than the voltage such that the PIC MCU’s IO2 pin “clamps” at approximately VDD.
...
8.4.1 POWER SUPPLY CONSIDERATIONS
The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-6 illustrates an appropriate bypass strategy.
In this example, the recommended bypass capacitor value is 0.1 μF. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
TECHNICAL DOCUMENTATION
..
Application Note Number Title Literature #
AN1080 Understanding Digital Potentiometers Resistor Variations DS01080
AN737 Using Digital Potentiometers to Design Low Pass Adjustable Filters DS00737
AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692
AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691
AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219
— Digital Potentiometer Design Guide DS22017
— Signal Chain Design Guide DS21825
MCP4151-503E/P MCP4151: Single Volatile 8-bit Potentiometer (HK$7.64, Element 14)
MCP4151-503E/XX: 50 kΩ, 8LD Device
IC, DGTL POT, SNGL, 50K, SPI, 8DIP; End To End Resistance:50kohm;
Track Taper:Linear; Resistance Tolerance:± 20%;
Supply Voltage Min:1.8V; Supply Voltage Max:5.5V;
Potentiometer IC Case Style:DIP; No. of Pins:8; No. of S
Device MCP4131: Single Volatile 7-bit Potentiometer
MCP4131T: Single Volatile 7-bit Potentiometer (Tape and Reel)
MCP4132: Single Volatile 7-bit Rheostat
MCP4132T: Single Volatile 7-bit Rheostat (Tape and Reel)
MCP4151: Single Volatile 8-bit Potentiometer
MCP4151T: Single Volatile 8-bit Potentiometer (Tape and Reel)
MCP4152: Single Volatile 8-bit Rheostat
MCP4152T: Single Volatile 8-bit Rheostat (Tape and Reel)
MCP4231: Dual Volatile 7-bit Potentiometer
MCP4231T: Dual Volatile 7-bit Potentiometer (Tape and Reel)
MCP4232: Dual Volatile 7-bit Rheostat
MCP4232T: Dual Volatile 7-bit Rheostat (Tape and Reel)
MCP4251: Dual Volatile 8-bit Potentiometer
MCP4251T: Dual Volatile 8-bit Potentiometer (Tape and Reel)
MCP4252: Dual Volatile 8-bit Rheostat
MCP4252T: Dual Volatile 8-bit
Resistance Version:
502 = 5 kΩ
103 = 10 kΩ
503 = 50 kΩ
104 = 100 kΩ
Temperature Range
I = -40°C to +85°C (Industrial)
E = -40°C to +125°C (Extended)
Package
MF = Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead
ML = Plastic Quad Flat No-lead (QFN), 16-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
P = Plastic Dual In-line (PDIP) (300 mil), 8/14-lead
SN = Plastic Small Outline (SOIC), (150 mil), 8-lead
SL = Plastic Small Outline (SOIC), (150 mil), 14-lead
ST = Plastic Thin Shrink Small Outline (TSSOP), 14-lead
UN = Plastic Micro Small Outline (MSOP), 10-lead
8-Lead PDIP
XXXXXXXX
XXXXXNNN
YYWW
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
...
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