Saturday, March 09, 2013
gz_test fitter report - Guzunty Pi
Fitter Report Design Name: gz_test Date: 1-12-2013, 10:19AM
https://raw.github.com/Guzunty/Pi/master/src/gz_test/gz_test.rpt
cpldfit: version P.40xd Xilinx Inc.
Fitter Report
Design Name: gz_test Date: 1-12-2013, 10:19AM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful
****************************** Device Pin Out *****************************
Device : XC9572XL-5-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-5-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 test_port_a<0> 23 GND
2 test_port_a<1> 24 test_port_c<3>
3 test_port_a<2> 25 test_port_c<5>
4 test_port_a<3> 26 test_port_c<6>
5 clk 27 test_port_c<7>
6 test_port_d<4> 28 test_port_d<0>
7 test_port_d<5> 29 test_port_d<1>
8 test_port_a<4> 30 TDO
9 test_port_a<5> 31 GND
10 GND 32 VCC
11 test_port_b<4> 33 test_port_d<2>
12 test_port_b<5> 34 test_port_d<3>
13 test_port_b<6> 35 test_port_a<6>
14 test_port_b<7> 36 test_port_a<7>
15 TDI 37 test_port_b<0>
16 TMS 38 test_port_b<1>
17 TCK 39 test_pin
18 test_port_c<0> 40 test_port_d<7>
19 test_port_c<1> 41 VCC
20 test_port_c<2> 42 test_port_d<6>
21 VCC 43 test_port_b<2>
22 test_port_c<4> 44 test_port_b<3>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
54 /72 ( 75%) 53 /360 ( 15%) 66 /216 ( 31%) 54 /72 ( 75%) 34 /34 (100%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 11/18 20/54 11/90 9/ 9*
FB2 9/18 6/54 9/90 9/ 9*
FB3 18/18* 20/54 18/90 9/ 9*
FB4 16/18 20/54 15/90 7/ 7*
----- ----- ----- -----
54/72 66/216 53/360 34/34
* - Resource is exhausted
** Global Control Resources **
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 0 0 | I/O : 28 28
Output : 33 33 | GCK/IO : 3 3
Bidirectional : 0 0 | GTS/IO : 2 2
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 34 34
** Power Data **
There are 54 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
use the default filename of 'gz_test.ise'.
************************* Summary of Mapped Logic ************************
** 33 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
test_port_a<0> 1 1 FB1_2 1~ I/O O STD FAST RESET
test_port_a<1> 1 1 FB1_5 2~ I/O O STD FAST RESET
test_port_a<2> 1 1 FB1_6 3~ I/O O STD FAST RESET
test_port_a<3> 1 1 FB1_8 4~ I/O O STD FAST RESET
test_port_d<4> 1 1 FB1_11 6 GCK/I/O O STD FAST RESET
test_port_d<5> 1 1 FB1_14 7 GCK/I/O O STD FAST RESET
test_port_a<4> 1 1 FB1_15 8~ I/O O STD FAST RESET
test_port_a<5> 1 1 FB1_17 9~ I/O O STD FAST RESET
test_port_a<6> 1 1 FB2_2 35~ I/O O STD FAST RESET
test_port_a<7> 1 1 FB2_5 36~ I/O O STD FAST RESET
test_port_b<0> 1 1 FB2_6 37~ I/O O STD FAST RESET
test_port_b<1> 1 1 FB2_8 38~ I/O O STD FAST RESET
test_pin 1 1 FB2_9 39 GSR/I/O O STD FAST RESET
test_port_d<7> 1 1 FB2_11 40 GTS/I/O O STD FAST RESET
test_port_d<6> 1 1 FB2_14 42 GTS/I/O O STD FAST RESET
test_port_b<2> 1 1 FB2_15 43~ I/O O STD FAST RESET
test_port_b<3> 1 1 FB2_17 44~ I/O O STD FAST RESET
test_port_b<4> 1 1 FB3_2 11~ I/O O STD FAST RESET
test_port_b<5> 1 1 FB3_5 12~ I/O O STD FAST RESET
test_port_b<6> 1 1 FB3_8 13~ I/O O STD FAST RESET
test_port_b<7> 1 1 FB3_9 14~ I/O O STD FAST RESET
test_port_c<0> 1 1 FB3_11 18~ I/O O STD FAST RESET
test_port_c<1> 1 1 FB3_14 19~ I/O O STD FAST RESET
test_port_c<2> 1 1 FB3_15 20~ I/O O STD FAST RESET
test_port_c<3> 1 1 FB3_16 24~ I/O O STD FAST RESET
test_port_c<4> 1 1 FB3_17 22~ I/O O STD FAST RESET
test_port_c<5> 1 1 FB4_2 25~ I/O O STD FAST RESET
test_port_c<6> 1 1 FB4_5 26~ I/O O STD FAST RESET
test_port_c<7> 1 1 FB4_8 27~ I/O O STD FAST RESET
test_port_d<0> 1 1 FB4_11 28~ I/O O STD FAST RESET
test_port_d<1> 1 1 FB4_14 29~ I/O O STD FAST RESET
test_port_d<2> 1 1 FB4_15 33~ I/O O STD FAST RESET
test_port_d<3> 1 1 FB4_17 34~ I/O O STD FAST RESET
** 21 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
counter<20> 1 20 FB1_13 STD RESET
counter<19> 1 19 FB1_16 STD RESET
counter<18> 1 18 FB1_18 STD RESET
counter<9> 1 9 FB3_1 STD RESET
counter<8> 1 8 FB3_3 STD RESET
counter<7> 1 7 FB3_4 STD RESET
counter<6> 1 6 FB3_6 STD RESET
counter<5> 1 5 FB3_7 STD RESET
counter<4> 1 4 FB3_10 STD RESET
counter<12> 1 12 FB3_12 STD RESET
counter<11> 1 11 FB3_13 STD RESET
counter<10> 1 10 FB3_18 STD RESET
counter<3> 1 3 FB4_4 STD RESET
counter<2> 1 2 FB4_6 STD RESET
counter<1> 1 1 FB4_7 STD RESET
counter<17> 1 17 FB4_9 STD RESET
counter<16> 1 16 FB4_10 STD RESET
counter<15> 1 15 FB4_12 STD RESET
counter<14> 1 14 FB4_13 STD RESET
counter<13> 1 13 FB4_16 STD RESET
counter<0> 0 0 FB4_18 STD RESET
** 1 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB1_9 5~ GCK/I/O GCK
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 20/34
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
test_port_a<0> 1 0 0 4 FB1_2 1~ I/O O
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
test_port_a<1> 1 0 0 4 FB1_5 2~ I/O O
test_port_a<2> 1 0 0 4 FB1_6 3~ I/O O
(unused) 0 0 0 5 FB1_7 (b)
test_port_a<3> 1 0 0 4 FB1_8 4~ I/O O
(unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK
(unused) 0 0 0 5 FB1_10 (b)
test_port_d<4> 1 0 0 4 FB1_11 6 GCK/I/O O
(unused) 0 0 0 5 FB1_12 (b)
counter<20> 1 0 0 4 FB1_13 (b) (b)
test_port_d<5> 1 0 0 4 FB1_14 7 GCK/I/O O
test_port_a<4> 1 0 0 4 FB1_15 8~ I/O O
counter<19> 1 0 0 4 FB1_16 (b) (b)
test_port_a<5> 1 0 0 4 FB1_17 9~ I/O O
counter<18> 1 0 0 4 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: counter<0> 8: counter<16> 15: counter<4>
2: counter<10> 9: counter<17> 16: counter<5>
3: counter<11> 10: counter<18> 17: counter<6>
4: counter<12> 11: counter<19> 18: counter<7>
5: counter<13> 12: counter<1> 19: counter<8>
6: counter<14> 13: counter<2> 20: counter<9>
7: counter<15> 14: counter<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
test_port_a<0> ....X................................... 1
test_port_a<1> .....X.................................. 1
test_port_a<2> ......X................................. 1
test_port_a<3> .......X................................ 1
test_port_d<4> ........X............................... 1
counter<20> XXXXXXXXXXXXXXXXXXXX.................... 20
test_port_d<5> .........X.............................. 1
test_port_a<4> ........X............................... 1
counter<19> XXXXXXXXXX.XXXXXXXXX.................... 19
test_port_a<5> .........X.............................. 1
counter<18> XXXXXXXXX..XXXXXXXXX.................... 18
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 6/48
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
test_port_a<6> 1 0 0 4 FB2_2 35~ I/O O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
test_port_a<7> 1 0 0 4 FB2_5 36~ I/O O
test_port_b<0> 1 0 0 4 FB2_6 37~ I/O O
(unused) 0 0 0 5 FB2_7 (b)
test_port_b<1> 1 0 0 4 FB2_8 38~ I/O O
test_pin 1 0 0 4 FB2_9 39 GSR/I/O O
(unused) 0 0 0 5 FB2_10 (b)
test_port_d<7> 1 0 0 4 FB2_11 40 GTS/I/O O
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 0 5 FB2_13 (b)
test_port_d<6> 1 0 0 4 FB2_14 42 GTS/I/O O
test_port_b<2> 1 0 0 4 FB2_15 43~ I/O O
(unused) 0 0 0 5 FB2_16 (b)
test_port_b<3> 1 0 0 4 FB2_17 44~ I/O O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: counter<13> 3: counter<15> 5: counter<19>
2: counter<14> 4: counter<16> 6: counter<20>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
test_port_a<6> ....X................................... 1
test_port_a<7> .....X.................................. 1
test_port_b<0> X....................................... 1
test_port_b<1> .X...................................... 1
test_pin .....X.................................. 1
test_port_d<7> .....X.................................. 1
test_port_d<6> ....X................................... 1
test_port_b<2> ..X..................................... 1
test_port_b<3> ...X.................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 20/34
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
counter<9> 1 0 0 4 FB3_1 (b) (b)
test_port_b<4> 1 0 0 4 FB3_2 11~ I/O O
counter<8> 1 0 0 4 FB3_3 (b) (b)
counter<7> 1 0 0 4 FB3_4 (b) (b)
test_port_b<5> 1 0 0 4 FB3_5 12~ I/O O
counter<6> 1 0 0 4 FB3_6 (b) (b)
counter<5> 1 0 0 4 FB3_7 (b) (b)
test_port_b<6> 1 0 0 4 FB3_8 13~ I/O O
test_port_b<7> 1 0 0 4 FB3_9 14~ I/O O
counter<4> 1 0 0 4 FB3_10 (b) (b)
test_port_c<0> 1 0 0 4 FB3_11 18~ I/O O
counter<12> 1 0 0 4 FB3_12 (b) (b)
counter<11> 1 0 0 4 FB3_13 (b) (b)
test_port_c<1> 1 0 0 4 FB3_14 19~ I/O O
test_port_c<2> 1 0 0 4 FB3_15 20~ I/O O
test_port_c<3> 1 0 0 4 FB3_16 24~ I/O O
test_port_c<4> 1 0 0 4 FB3_17 22~ I/O O
counter<10> 1 0 0 4 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: counter<0> 8: counter<17> 15: counter<4>
2: counter<10> 9: counter<18> 16: counter<5>
3: counter<11> 10: counter<19> 17: counter<6>
4: counter<13> 11: counter<1> 18: counter<7>
5: counter<14> 12: counter<20> 19: counter<8>
6: counter<15> 13: counter<2> 20: counter<9>
7: counter<16> 14: counter<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
counter<9> X.........X.XXXXXXX..................... 9
test_port_b<4> .......X................................ 1
counter<8> X.........X.XXXXXX...................... 8
counter<7> X.........X.XXXXX....................... 7
test_port_b<5> ........X............................... 1
counter<6> X.........X.XXXX........................ 6
counter<5> X.........X.XXX......................... 5
test_port_b<6> .........X.............................. 1
test_port_b<7> ...........X............................ 1
counter<4> X.........X.XX.......................... 4
test_port_c<0> ...X.................................... 1
counter<12> XXX.......X.XXXXXXXX.................... 12
counter<11> XX........X.XXXXXXXX.................... 11
test_port_c<1> ....X................................... 1
test_port_c<2> .....X.................................. 1
test_port_c<3> ......X................................. 1
test_port_c<4> .......X................................ 1
counter<10> X.........X.XXXXXXXX.................... 10
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 20/34
Number of signals used by logic mapping into function block: 20
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 (b)
test_port_c<5> 1 0 0 4 FB4_2 25~ I/O O
(unused) 0 0 0 5 FB4_3 (b)
counter<3> 1 0 0 4 FB4_4 (b) (b)
test_port_c<6> 1 0 0 4 FB4_5 26~ I/O O
counter<2> 1 0 0 4 FB4_6 (b) (b)
counter<1> 1 0 0 4 FB4_7 (b) (b)
test_port_c<7> 1 0 0 4 FB4_8 27~ I/O O
counter<17> 1 0 0 4 FB4_9 (b) (b)
counter<16> 1 0 0 4 FB4_10 (b) (b)
test_port_d<0> 1 0 0 4 FB4_11 28~ I/O O
counter<15> 1 0 0 4 FB4_12 (b) (b)
counter<14> 1 0 0 4 FB4_13 (b) (b)
test_port_d<1> 1 0 0 4 FB4_14 29~ I/O O
test_port_d<2> 1 0 0 4 FB4_15 33~ I/O O
counter<13> 1 0 0 4 FB4_16 (b) (b)
test_port_d<3> 1 0 0 4 FB4_17 34~ I/O O
counter<0> 0 0 0 5 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: counter<0> 8: counter<16> 15: counter<4>
2: counter<10> 9: counter<18> 16: counter<5>
3: counter<11> 10: counter<19> 17: counter<6>
4: counter<12> 11: counter<1> 18: counter<7>
5: counter<13> 12: counter<20> 19: counter<8>
6: counter<14> 13: counter<2> 20: counter<9>
7: counter<15> 14: counter<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
test_port_c<5> ........X............................... 1
counter<3> X.........X.X........................... 3
test_port_c<6> .........X.............................. 1
counter<2> X.........X............................. 2
counter<1> X....................................... 1
test_port_c<7> ...........X............................ 1
counter<17> XXXXXXXX..X.XXXXXXXX.................... 17
counter<16> XXXXXXX...X.XXXXXXXX.................... 16
test_port_d<0> ....X................................... 1
counter<15> XXXXXX....X.XXXXXXXX.................... 15
counter<14> XXXXX.....X.XXXXXXXX.................... 14
test_port_d<1> .....X.................................. 1
test_port_d<2> ......X................................. 1
counter<13> XXXX......X.XXXXXXXX.................... 13
test_port_d<3> .......X................................ 1
counter<0> ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FTCPE_counter0: FTCPE port map (counter(0),'1',clk,'0','0');
FTCPE_counter1: FTCPE port map (counter(1),counter(0),clk,'0','0');
FTCPE_counter2: FTCPE port map (counter(2),counter_T(2),clk,'0','0');
counter_T(2) <= (counter(0) AND counter(1));
FTCPE_counter3: FTCPE port map (counter(3),counter_T(3),clk,'0','0');
counter_T(3) <= (counter(0) AND counter(1) AND counter(2));
FTCPE_counter4: FTCPE port map (counter(4),counter_T(4),clk,'0','0');
counter_T(4) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3));
FTCPE_counter5: FTCPE port map (counter(5),counter_T(5),clk,'0','0');
counter_T(5) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3) AND counter(4));
FTCPE_counter6: FTCPE port map (counter(6),counter_T(6),clk,'0','0');
counter_T(6) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5));
FTCPE_counter7: FTCPE port map (counter(7),counter_T(7),clk,'0','0');
counter_T(7) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5) AND counter(6));
FTCPE_counter8: FTCPE port map (counter(8),counter_T(8),clk,'0','0');
counter_T(8) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5) AND counter(6) AND
counter(7));
FTCPE_counter9: FTCPE port map (counter(9),counter_T(9),clk,'0','0');
counter_T(9) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5) AND counter(6) AND
counter(7) AND counter(8));
FTCPE_counter10: FTCPE port map (counter(10),counter_T(10),clk,'0','0');
counter_T(10) <= (counter(0) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5) AND counter(6) AND
counter(7) AND counter(8) AND counter(9));
FTCPE_counter11: FTCPE port map (counter(11),counter_T(11),clk,'0','0');
counter_T(11) <= (counter(0) AND counter(10) AND counter(1) AND
counter(2) AND counter(3) AND counter(4) AND counter(5) AND
counter(6) AND counter(7) AND counter(8) AND counter(9));
FTCPE_counter12: FTCPE port map (counter(12),counter_T(12),clk,'0','0');
counter_T(12) <= (counter(0) AND counter(10) AND counter(11) AND
counter(1) AND counter(2) AND counter(3) AND counter(4) AND
counter(5) AND counter(6) AND counter(7) AND counter(8) AND
counter(9));
FTCPE_counter13: FTCPE port map (counter(13),counter_T(13),clk,'0','0');
counter_T(13) <= (counter(0) AND counter(10) AND counter(11) AND
counter(12) AND counter(1) AND counter(2) AND counter(3) AND
counter(4) AND counter(5) AND counter(6) AND counter(7) AND
counter(8) AND counter(9));
FTCPE_counter14: FTCPE port map (counter(14),counter_T(14),clk,'0','0');
counter_T(14) <= (counter(0) AND counter(13) AND counter(10) AND
counter(11) AND counter(12) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5) AND counter(6) AND
counter(7) AND counter(8) AND counter(9));
FTCPE_counter15: FTCPE port map (counter(15),counter_T(15),clk,'0','0');
counter_T(15) <= (counter(0) AND counter(13) AND counter(14) AND
counter(10) AND counter(11) AND counter(12) AND counter(1) AND
counter(2) AND counter(3) AND counter(4) AND counter(5) AND
counter(6) AND counter(7) AND counter(8) AND counter(9));
FTCPE_counter16: FTCPE port map (counter(16),counter_T(16),clk,'0','0');
counter_T(16) <= (counter(0) AND counter(13) AND counter(14) AND
counter(15) AND counter(10) AND counter(11) AND counter(12) AND
counter(1) AND counter(2) AND counter(3) AND counter(4) AND
counter(5) AND counter(6) AND counter(7) AND counter(8) AND
counter(9));
FTCPE_counter17: FTCPE port map (counter(17),counter_T(17),clk,'0','0');
counter_T(17) <= (counter(0) AND counter(13) AND counter(14) AND
counter(15) AND counter(16) AND counter(10) AND counter(11) AND
counter(12) AND counter(1) AND counter(2) AND counter(3) AND
counter(4) AND counter(5) AND counter(6) AND counter(7) AND
counter(8) AND counter(9));
FTCPE_counter18: FTCPE port map (counter(18),counter_T(18),clk,'0','0');
counter_T(18) <= (counter(0) AND counter(13) AND counter(14) AND
counter(15) AND counter(16) AND counter(17) AND counter(10) AND
counter(11) AND counter(12) AND counter(1) AND counter(2) AND
counter(3) AND counter(4) AND counter(5) AND counter(6) AND
counter(7) AND counter(8) AND counter(9));
FTCPE_counter19: FTCPE port map (counter(19),counter_T(19),clk,'0','0');
counter_T(19) <= (counter(0) AND counter(13) AND counter(14) AND
counter(15) AND counter(16) AND counter(17) AND counter(18) AND
counter(10) AND counter(11) AND counter(12) AND counter(1) AND
counter(2) AND counter(3) AND counter(4) AND counter(5) AND
counter(6) AND counter(7) AND counter(8) AND counter(9));
FTCPE_counter20: FTCPE port map (counter(20),counter_T(20),clk,'0','0');
counter_T(20) <= (counter(0) AND counter(13) AND counter(14) AND
counter(15) AND counter(16) AND counter(17) AND counter(18) AND
counter(19) AND counter(10) AND counter(11) AND counter(12) AND
counter(1) AND counter(2) AND counter(3) AND counter(4) AND
counter(5) AND counter(6) AND counter(7) AND counter(8) AND
counter(9));
FDCPE_test_pin: FDCPE port map (test_pin,counter(20),clk,'0','0');
FDCPE_test_port_a0: FDCPE port map (test_port_a(0),counter(13),clk,'0','0');
FDCPE_test_port_a1: FDCPE port map (test_port_a(1),counter(14),clk,'0','0');
FDCPE_test_port_a2: FDCPE port map (test_port_a(2),counter(15),clk,'0','0');
FDCPE_test_port_a3: FDCPE port map (test_port_a(3),counter(16),clk,'0','0');
FDCPE_test_port_a4: FDCPE port map (test_port_a(4),counter(17),clk,'0','0');
FDCPE_test_port_a5: FDCPE port map (test_port_a(5),counter(18),clk,'0','0');
FDCPE_test_port_a6: FDCPE port map (test_port_a(6),counter(19),clk,'0','0');
FDCPE_test_port_a7: FDCPE port map (test_port_a(7),counter(20),clk,'0','0');
FDCPE_test_port_b0: FDCPE port map (test_port_b(0),counter(13),clk,'0','0');
FDCPE_test_port_b1: FDCPE port map (test_port_b(1),counter(14),clk,'0','0');
FDCPE_test_port_b2: FDCPE port map (test_port_b(2),counter(15),clk,'0','0');
FDCPE_test_port_b3: FDCPE port map (test_port_b(3),counter(16),clk,'0','0');
FDCPE_test_port_b4: FDCPE port map (test_port_b(4),counter(17),clk,'0','0');
FDCPE_test_port_b5: FDCPE port map (test_port_b(5),counter(18),clk,'0','0');
FDCPE_test_port_b6: FDCPE port map (test_port_b(6),counter(19),clk,'0','0');
FDCPE_test_port_b7: FDCPE port map (test_port_b(7),counter(20),clk,'0','0');
FDCPE_test_port_c0: FDCPE port map (test_port_c(0),counter(13),clk,'0','0');
FDCPE_test_port_c1: FDCPE port map (test_port_c(1),counter(14),clk,'0','0');
FDCPE_test_port_c2: FDCPE port map (test_port_c(2),counter(15),clk,'0','0');
FDCPE_test_port_c3: FDCPE port map (test_port_c(3),counter(16),clk,'0','0');
FDCPE_test_port_c4: FDCPE port map (test_port_c(4),counter(17),clk,'0','0');
FDCPE_test_port_c5: FDCPE port map (test_port_c(5),counter(18),clk,'0','0');
FDCPE_test_port_c6: FDCPE port map (test_port_c(6),counter(19),clk,'0','0');
FDCPE_test_port_c7: FDCPE port map (test_port_c(7),counter(20),clk,'0','0');
FDCPE_test_port_d0: FDCPE port map (test_port_d(0),counter(13),clk,'0','0');
FDCPE_test_port_d1: FDCPE port map (test_port_d(1),counter(14),clk,'0','0');
FDCPE_test_port_d2: FDCPE port map (test_port_d(2),counter(15),clk,'0','0');
FDCPE_test_port_d3: FDCPE port map (test_port_d(3),counter(16),clk,'0','0');
FDCPE_test_port_d4: FDCPE port map (test_port_d(4),counter(17),clk,'0','0');
FDCPE_test_port_d5: FDCPE port map (test_port_d(5),counter(18),clk,'0','0');
FDCPE_test_port_d6: FDCPE port map (test_port_d(6),counter(19),clk,'0','0');
FDCPE_test_port_d7: FDCPE port map (test_port_d(7),counter(20),clk,'0','0');
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572XL-5-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-5-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 test_port_a<0> 23 GND
2 test_port_a<1> 24 test_port_c<3>
3 test_port_a<2> 25 test_port_c<5>
4 test_port_a<3> 26 test_port_c<6>
5 clk 27 test_port_c<7>
6 test_port_d<4> 28 test_port_d<0>
7 test_port_d<5> 29 test_port_d<1>
8 test_port_a<4> 30 TDO
9 test_port_a<5> 31 GND
10 GND 32 VCC
11 test_port_b<4> 33 test_port_d<2>
12 test_port_b<5> 34 test_port_d<3>
13 test_port_b<6> 35 test_port_a<6>
14 test_port_b<7> 36 test_port_a<7>
15 TDI 37 test_port_b<0>
16 TMS 38 test_port_b<1>
17 TCK 39 test_pin
18 test_port_c<0> 40 test_port_d<7>
19 test_port_c<1> 41 VCC
20 test_port_c<2> 42 test_port_d<6>
21 VCC 43 test_port_b<2>
22 test_port_c<4> 44 test_port_b<3>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-5-PC44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
Input Limit : 54
Pterm Limit : 25
.END
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