EEPROM 25LC320 summary

MicroChip SPI 2MHz EEPROM 25LC320


Microchip 25LC320 (2MH)  32K SPI Bus Serial EEPROM

Features:

• Low-power CMOS technology:

- Write current: 3 mA maximum

- Read current: 500 μA typical

- Standby current: 500 nA typical

• 4096 x 8 bit organization

• 32 byte page

• Write cycle time: 5 ms maximum

• Self-timed erase and write cycles

• Block write protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection:

- Power on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability:

- Endurance: 1M E/W cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• 8-pin PDIP, SOIC and TSSOP packages

• 14-lead TSSOP package

• Temperature ranges supported:


Description:

The Microchip Technology Inc. 25AA320/25LC320/25C320 (25XX320*) are 32 Kbit serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input.

Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts.



3.0 FUNCTIONAL DESCRIPTION

3.1 Principles Of Operation

The 25XX320 are 4096 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software.

The 25XX320 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation.

Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX320 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.

3.2 Read Sequence

The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX320 followed by the 16-bit address, with the four MSBs of the address being don’t care bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (0FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 3-1).

3.3 Write Sequence

Prior to any attempt to write data to the 25XX320, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX320. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set.

Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the four MSBs of the address being don’t care bits, and then the data to be written. Up to 32 bytes of data can be sent to the 25XX320 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with xxxx xxxx xxx0 0000 and ends with xxxx xxxx xxx1 1111.

If the internal address counter reaches xxxx xxxx xxx1 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the least significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

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