CPLD XC9572XL learning notes

I always wondered the use of GCK/GSR.GTS.  So I googled.


Xilinx CPLDs: XC9500 vs CoolRunner-II - dangerousprototypes.com

http://dangerousprototypes.com/docs/Xilinx_CPLDs:_XC9500_vs_CoolRunner-II

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Special features

There are also some pins with special features, though they are not used unless specifically enabled in the CPLD synthesis:

GCK (global clock) - optimized to distribute a clock signal to all macrocells with minimum skew and extra resources

GSR (global set reset) - optimized path to the Set/Reset signal of all macrocells, allows synchronous reset of the flip-flop in all cells with minimum extra resources

GTS (global tri-state) - optimized to put all CPLD pins in a high impedance state

• Programmable logic quick start UG500

• XC9500XL user guide

• CoolRunner-II user guide

• 5volt IO with the CoolRunner-II

• GCK, GTS, and GSR help

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