MCP3201 learning notes

Now I am reading the MCP3201 datasheet.

MciroChip MCP3201 2.7V 12-Bit A/D Converter with SPI Serial Interface

Features

• 12-Bit Resolution

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3201-B)

• ±2 LSB max INL (MCP3201-C)

• On-chip Sample and Hold

• SPI Serial Interface (modes 0,0 and 1,1)

• Single Supply Operation: 2.7V - 5.5V

• 100 ksps Maximum Sampling Rate at VDD = 5V

• 50 ksps Maximum Sampling Rate at VDD = 2.7V

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Description

The Microchip Technology MCP3201 device is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The device provides a single pseudo-differential input. Differential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of sample rates of up to 100 ksps at a clock rate of 1.6 MHz. The MCP3201 device operates over a broad voltage range (2.7V-5.5V).

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3.1 Positive Analog Input (IN+)

Positive analog input. This input can vary from IN- to VREF + IN-.

3.2 Negative Analog Input (IN-)

Negative analog input. This input can vary ±100 mV from VSS.

3.3 Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.

3.4 Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place.
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3.5 Serial Data Output (DOUT)

The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.

4.0 DEVICE OPERATION

The MCP3201 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock after CS has been pulled low. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3201 device.

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5.0 SERIAL COMMUNICATIONS

Communication with the device is done using a standard SPI-compatible serial interface.

Initiating communication with the MCP3201 device begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication.

The device will begin to sample the analog input on the first rising edge after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit.

The next 12 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock.

If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely.

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3201 Device with Microcontroller SPI Ports

With most microcontroller SPI ports, it is required to clock out eight bits at a time. If this is the case, it will be necessary to provide more clocks than are required for the MCP3201.

As an example, Figure 6-1 and Figure 6-2 show how the MCP3201 device can be interfaced to a microcontroller with a standard SPI port.

Since the MCP3201 always clocks data out on the falling edge of clock, the MCU SPI port must be configured to match this operation. SPI Mode 0,0 (clock idles low) and SPI Mode 1,1 (clock idles high) are both compatible with the MCP3201. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the CLK from the microcontroller idles in the ‘low’ state.

As shown in the diagram, the MSB is clocked out of the A/D Converter on the falling edge of the third clock pulse. After the first eight clocks have been sent to the device, the microcontroller’s receive buffer will contain two unknown bits (the output is at high-impedance for the first two clocks), the null bit and the highest order five bits of the conversion. After the second eight clocks have been sent to the device, the MCU receive register will contain the lowest-order seven bits and the B1 bit repeated as the A/D Converter has begun to shift out LSB first data with the extra clock. Typical procedure would then call for the lower-order byte of data to be shifted right by one bit to remove the extra B1 bit. The B7 bit is then transferred from the high-order byte to the lower-order byte, and then the higher-order byte is shifted one bit to the right as well. Easier manipulation of the converted data can be obtained by using this method.

Figure 6-2 shows the same thing in SPI Mode 1,1 which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock.



6.2 Maintaining Minimum Clock Speed

When the MCP3201 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst-case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met.

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