SPI modes reading notes

I have never paid attention to the confusing thing of SPI modes.  But now I need to troubleshoot EEPROM and I need to make sure if the RPi SPI mode matches that of MicroChip.  So I wikied.



SPI Clock polarity and phase - Wikipedia

http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

A timing diagram showing clock polarity and phase. The red vertical line represents CPHA=0 and the blue vertical line represents CPHA=1

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide[3] names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.

The timing diagram is shown [above]. The timing is further described below and applies to both the master and the slave device.

At CPOL=0 the base value of the clock is zero

For CPHA=0, data is captured on the clock's rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition).

For CPHA=1, data is captured on the clock's falling edge and data is propagated on a rising edge.

At CPOL=1 the base value of the clock is one (inversion of CPOL=0)

For CPHA=0, data is captured on clock's falling edge and data is propagated on a rising edge.

For CPHA=1, data is captured on clock's rising edge and data is propagated on a falling edge.

That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active.

The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle.

This adds more flexibility to the communication channel between the master and slave.

Some products use different naming conventions. For example, the TI MSP430 uses the name UCCKPL instead of CPOL, and its UCCKPH is the inverse of CPHA. When connecting two chips together, carefully examine the clock phase initialization values to be sure of using the right settings.

Mode numbers

The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit:

Mode CPOL CPHA

0 0 0
1 0 1
2 1 0
3 1 1

Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1

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