So I am coming back to Guzunty Pi. This time I will play with the 8p8i. I skimmed through the basic documents before reading the sample C program.
Guzunty Pi gz_8p8i waveform - Last edited by campbellsan, 13 days ago 2013masr25
https://github.com/Guzunty/Pi/wiki/gz_8p8i-waveform
In this core, the inputs work like they do in ordinary IO cores, but the 'pwms' output bus switches each bit dynamically between logic '1' and logic '0' as an internal counter passes the value of a cached value for each pwm output bit. When the internal counter rolls over, the output bits are set back to logic '1' and the cycle repeats.
To control the PWM outputs, write a pwm number (0 - 7) to the SPI bus followed by a duty cycle value (0 - 32).
If you look at the upper three signals in the waveform display you will see where the testbench (i.e. the CPU when running in circuit) is stimulating the core. Note that the stimulation ends about halfway across, and that the core activity continues modulating the pulsed output. To support this, the core needs its own clock. In the Guzunty Pi, we use one of the GPIO special out functions (GPCLK0 on GPIO4). The Pi hardware clock output is wired to the 'clk' signal seen in this waveform. It is switching too fast to see the clock as anything other than a stippled band at the resolution of this image.
The resource usage in the fitter report reveals a point worthy of discussion. The resource usage for this core is extremely high (Macrocells 96%, Registers 83%). Why? The reason is that this design needs to cache a lot of data, 40 bits just for the individual pwm duty cycle registers. CPLD's don't make great RAM chips. There is only one bit of set/reset storage per Macrocell, we need 40 bits and there are only 72 macrocells in the whole device (and we still
need registers for other purposes such as the internal counter).
cpldfit: version P.40xd Xilinx Inc.
Fitter Report
Design Name: gz_8p8i Date: 1- 6-2013, 11:00AM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
69 /72 ( 96%) 262 /360 ( 73%) 103/216 ( 48%) 60 /72 ( 83%) 21 /34 ( 62%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/18 37/54 77/90 8/ 9
FB2 17/18 28/54 65/90 3/ 9
FB3 18/18* 20/54 60/90 4/ 9
FB4 18/18* 18/54 60/90 6/ 7
----- ----- ----- -----
69/72 103/216 262/360 21/34
* - Resource is exhausted
...
************************* Summary of Mapped Logic ************************
** 9 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
pwms<0> 3 7 FB1_2 1 I/O O STD FAST RESET
pwms<1> 3 7 FB1_5 2 I/O O STD FAST RESET
pwms<2> 3 7 FB1_6 3 I/O O STD FAST RESET
pwms<3> 3 7 FB1_8 4 I/O O STD FAST RESET
pwms<4> 3 7 FB1_15 8 I/O O STD FAST RESET
pwms<5> 3 7 FB1_17 9 I/O O STD FAST RESET
pwms<6> 3 7 FB2_2 35 I/O O STD FAST RESET
pwms<7> 3 7 FB2_5 36 I/O O STD FAST RESET
miso 9 12 FB4_17 34 I/O O STD FAST
...
** 12 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
inputs<6> FB1_11 6~ GCK/I/O I
inputs<7> FB1_14 7~ GCK/I/O I
clk FB2_6 37 I/O I
inputs<0> FB3_14 19 I/O I
inputs<1> FB3_15 20 I/O I
inputs<2> FB3_16 24 I/O I
inputs<3> FB3_17 22 I/O I
inputs<4> FB4_2 25 I/O I
inputs<5> FB4_5 26 I/O I
sclk FB4_11 28 I/O I
mosi FB4_14 29 I/O I
sel FB4_15 33 I/O I
****************************** Device Pin Out *****************************
Device : XC9572XL-5-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9572XL-5-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 pwms<0> 23 GND
2 pwms<1> 24 inputs<2>
3 pwms<2> 25 inputs<4>
4 pwms<3> 26 inputs<5>
5 KPR 27 KPR
6 inputs<6> 28 sclk
7 inputs<7> 29 mosi
8 pwms<4> 30 TDO
9 pwms<5> 31 GND
10 GND 32 VCC
11 KPR 33 sel
12 KPR 34 miso
13 KPR 35 pwms<6>
14 KPR 36 pwms<7>
15 TDI 37 clk
16 TMS 38 KPR
17 TCK 39 KPR
18 KPR 40 KPR
19 inputs<0> 41 VCC
20 inputs<1> 42 KPR
21 VCC 43 KPR
22 inputs<3> 44 KPR
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
...
.END
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